Search documents

Browse topics

Document details

How to Deal with Thin Wafers in a Heterojunction Solar Cells Industrial Pilot Line: First Analysis of the Integration of Cells Down to 70µm Thick in Production Mode
S. Harrison, O. Nos, A. Danel, D. Muñoz, J.P. Rakotoniaina, J. Gaume, C. Roux, P.J. Ribeyron
Heterojunction, Thin Wafer, Pilot Line, Smart Wire, Amorphous Silicon
Wafer-Based Silicon Solar Cells and Materials Technology
Subtopic: Manufacturing and Processing
Event: 32nd European Photovoltaic Solar Energy Conference and Exhibition
Session: 2BO.9.2
358 - 362
ISBN: 3-936338-41-8
Paper DOI: 10.4229/EUPVSEC20162016-2BO.9.2
0,00 EUR
Document(s): paper


In this paper we present the first results obtained at CEA-INES for the integration of thin and ultra-thin silicon wafers in the current silicon heterojunction (SHJ) LabFab Pilot Line production flow. Impact of the cell thickness reduction on final device characteristics is first detailed. Then overall compatibility of such wafers with current production constraints and actual equipment’s configuration is analyzed, identifying main breakage and throughput issues. Finally, improvement paths are proposed to enhance both efficiencies and reliability on the overall cell fabrication flow demonstrating also the potential compatibility of current SHJ production line for wafers as thin as 80μm.