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Title:
 
The Performance of Cast Mono Wafer, Cell and Module
 
Author(s):
 
X.-S. Wang, S. Zhou, Y. Gu, Z. Xing, T. Galvez
 
Keywords:
 
Dislocation, Grain Boundary, MCCE, Cast Mono
 
Topic:
 
Silicon Cells
Subtopic: Feedstock, Crystallisation, Wafering, Defect Engineering
Event: 35th European Photovoltaic Solar Energy Conference and Exhibition
Session: 2AV.1.35
 
Pages:
 
543 - 547
ISBN: 3-936338-50-7
Paper DOI: 10.4229/35thEUPVSEC20182018-2AV.1.35
 
Price:
 
 
0,00 EUR
 
Document(s): paper, poster
 

Abstract/Summary:


Cast mono (quasi mono or mono-like) material is gaining attention in photovoltaic industry due to its potential to reach high efficiency close to p-type mono while keeping the cost level close to multi. Nevertheless, there still remain challenges to industrialize the technology. One is how to control the brick quality, to keep the mono percentage as high as possible, another is how to treat the outlier wafer during cell texturing which will result in very shiny parts and be rejected by the end customers. The cost should also be considered nowadays as photovoltaic is a cost driven industry. The good news are we developed a suitable casting process which the mono percentage reaches 90% and we are using metal catalyzed chemical etching (MCCE) texturing process to create black silicon for the outlier wafer. The solutions we carried out paves the way for the cast mono technology. G5 cast mono brick is grown using ECM Crystalmax furnace by a special seed arrangement and corresponding recipe. The brick quality is greatly improved due to lack of grain boundaries (GB). The defect multiplication is also carefully controlled. The brick is squared, cropped, polished and cut into wafers using diamond wire sawing (DWS). The wafers are sorted by the center, the edge and the corner location to study different behavior. For the center wafers, as it is very close to mono, the alkaline texture and standard PERC process is applied. The cell efficiency reaches 20.9% average due to better lifetime. For the wafers from the edge and the corner, the MCCE texture and standard PERC process is using. The efficiency reaches 20.2% for edge and 19.7% for the corner due to lower light trapping. The cells have very uniform outlook without any shiny parts thanks to the black silicon treatment on the surface. Modules were made using the produced center cells. Max module power output reaches 370 watts using 144 half-cell designs. The power is quite promising which makes the product competitive on the market. Characterization from brick to wafer, cell and module were also carried out in this paper to verify the performance and give possible explanations.